MOS (metal-oxide-semiconductor lamination) field effect transistors are widely used as basic components in semiconductor devices.
ICs (integrated circuits) with high breakdown voltages use MOS transistors with medium-high drive voltages, for example, about 10–20 V (referred to as MOS transistors with high breakdown voltages hereinafter).
A type of MOS transistor with a high breakdown voltage and double sidewall insulation films on both sides of the gate electrode has been proposed to achieve compatibility in the manufacturing process with MOS transistors with low drive voltages.
FIG. 12 is a cross-sectional view illustrating a semiconductor device of the aforementioned conventional example.
A first gate insulation film 111 made of silicon oxide is formed in an active area forming the first channel creation area of the p-type semiconductor substrate 110, which is partitioned by component separating insulation film 140. A first gate electrode 112 made of polysilicon is formed on this gate insulation film.
First inner sidewall insulation film 114 and first outer sidewall insulation film 116 made of silicon oxide are formed on both sides of the first gate electrode 112.
A first lightly doped area 113 containing an n-type impurity at a low concentration is formed adjacent to the first channel creation area in semiconductor substrate 110 in the area underneath the first inner sidewall insulation film 114.
A first high-concentration area 115 containing an n-type impurity at a high concentration is formed adjacent to the first lightly doped area 113 in semiconductor substrate 110 in the area underneath the first outer sidewall insulation film 116 and in the bordering area of the substrate.
In this way, a MOS transistor TR1 with a low drive voltage is formed.
In contrast, a second gate insulation film 121 made of silicon oxide is formed in an active area forming the second channel creation area of the p-type semiconductor substrate 110, which is partitioned by component separating insulation film 140. A second gate electrode 122 made of polysilicon is formed on this gate insulation film.
Second inner sidewall insulation film 125 and second outer sidewall insulation film 126 are formed on both sides of the second gate electrode 122.
A second lightly doped area 123 containing an n-type impurity at a low concentration is formed adjacent to the second channel creation area in semiconductor substrate 110 in the area underneath the second inner sidewall insulation film 125 and the second outer sidewall insulation film 126.
A second heavily doped area 127 containing an n-type impurity at a high concentration is formed adjacent to the second lightly doped area 123 in semiconductor substrate 110 in the area underneath the two sides of the second outer sidewall insulation film 126.
A third low-concentration area 124 containing an n-type impurity at a lower concentration than the second lightly doped area 123 is formed in such a way that it is deeper than the second lightly doped area 123 and the second heavily doped area 127 and it extends into the second channel creation area farther than the end of the second lightly doped area 123 on the side of the second channel creation area.
In this way, a MOS transistor TR2 with a high breakdown voltage and a medium-high drive voltage, for example, about 10–20 V is formed.
The aforementioned semiconductor device, for example, is manufactured as follows.
First, the first gate insulation film 111 is formed in the first transistor fabrication area having the first channel creation area on p-type semiconductor substrate 110 and the second gate insulation film 121 is formed in the second transistor fabrication area.
Then, the first gate electrode 112 is formed on the first gate insulation film 111 and the second gate electrode 122 is formed on the second gate insulation film 121.
Subsequently, a low concentration of n-type impurity ions is injected into the first transistor fabrication area with the first gate electrode 112 used as a mask to form the first lightly doped area 113.
Subsequently, n-type impurity ions are injected into the second transistor fabrication area with the second gate electrode 122 used as a mask to form the second lightly doped area 123. Also, the third low-concentration impurity 124 is formed by ions injected into the semiconductor substrate obliquely, for example, at an angle of 45°.
Subsequently, silicon oxide is deposited on the entire surface using, for example, the CVD method. Then, the entire surface is etched to form the first inner sidewall insulation film 114 on both sides of the first gate electrode 112 and to form the second inner sidewall insulation film 125 on both sides of the second gate electrode 122.
Subsequently, a high concentration of n-type impurity ions is injected into the first transistor fabrication area with the first inner sidewall insulation film 114 used as a mask to form the first heavily doped area 115.
Subsequently, silicon oxide is deposited on the entire surface using, for example, the CVD method. Then, the entire surface is etched to form the first outer sidewall insulation film 116 on both sides of the first inner sidewall insulation film 114 and to form the second outer sidewall insulation film 126 on both sides of the second inner sidewall insulation film 125.
Subsequently, n-type impurity ions are injected into the second transistor fabrication area with the second inner sidewall insulation film 125 and the second outer sidewall insulation film 126 used as a mask to form the second heavily doped area 127.
In this way, the semiconductor device with the configuration shown in FIG. 12 can be manufactured.
However, for MOS transistors with high breakdown voltages having double sidewall insulation films for compatibility in the manufacturing process with MOS transistors for low drive voltages during the etching performed to form the second inner sidewall insulation film 125 on both sides of the second gate electrode 122, the naked substrate is exposed or the surface layer of the substrate is removed. This has a negative effect on the electric characteristics, as described later.
This problem is common to n-channel type and p-channel type MOS transistors with high breakdown voltages.
First of all, when a positive drain voltage VD is applied, the gate voltage VG in the aforementioned MOS transistors with high breakdown voltages becomes 0 V and the drain leakage current becomes large.
FIG. 13(A) is a schematic cross-sectional view illustrating the expanded source-drain area. During the etching performed to form the second inner sidewall insulation film 125 on both sides of the second gate electrode 122, semiconductor substrate 110 is exposed or the surface layer is removed. As a result, regions with defects/contaminants DC are formed in the second lightly doped area 123 due to the introduction of lattice defects or contaminants.
FIG. 13(B) is a schematic diagram illustrating the energy band in the channel direction on the cross section shown in FIG. 13(A). It shows the conduction band Ec and valence band Ev of each area of the semiconductor substrate 10, the third lightly doped area 124, the second lightly doped area 123, and the second heavily doped area 127. Due to the formation of the regions with defects/contaminants DC in the second lightly doped area 123 as described above, an allowed energy state is formed in the forbidden band. This energy state becomes the recombination/generation center RGC. The recombination/generation center RGC becomes the medium for generation of electron-hole pairs. The number of electron-hole pairs increases exponentially compared with the case where there is no recombination/generation center RGC. The generated electrons e and holes h move in opposite directions due to the electric field in the depletion layer of the reverse biased second lightly doped area 123 and becomes a drift current, which is observed as the drain leakage current.
Exposure of the substrate or removal of the surface layer also occurs in the second heavily doped area 127, which leads to the formation of a region with defects/contaminants DC that becomes a recombination/generation center RGC. However, since the concentration of the impurity is very high, the electric field in the lateral direction in this area is very small, so there is no substantial contribution to the drain leakage current.
Second of all, if the aforementioned MOS transistors with high breakdown voltages are connected in series by the lightly doped areas of the transistors, the cutoff source voltage becomes low.
FIG. 14(A) is a cross-sectional view illustrating two MOS transistors (TR2a, TR2b) that have high breakdown voltages and that are connected in series by the lightly doped areas.
Each of the MOS transistors (TR2a, TR2b) with high breakdown voltages has the same configuration as MOS transistor TR2 with a high breakdown voltage shown in FIG. 12. However, the second heavily doped area is not formed in the region where the two MOS transistors (TR2a, TR2b) with high breakdown voltages are connected in series. There are only the second lightly doped area 123 and the third lightly doped area 124.
FIG. 14(B) shows the equivalent circuit of the configuration shown in FIG. 14(A). The MOS transistors (TR2a, TR2b) with high breakdown voltages are formed in the substrate B having a channel creation area and have gate electrodes (G1, G2), respectively. The heavily doped area of one MOS transistor TR2a with a high breakdown voltage becomes drain D, while the heavily doped area of the other MOS transistor TR2b with a high breakdown voltage becomes source S.
In the aforementioned configuration, when a high drain-substrate voltage VDB is applied, the drain current becomes small, and the apparent substrate effect becomes high. This is because the area with the highest impurity concentration in the surface layer of the second lightly doped area 123 in the region where the two MOS transistors (TR2a, TR2b) with high breakdown voltages are connected is removed by etching and becomes a high-resistance area. When the drain-substrate voltage VDB is further increased, the depletion layer V of the pn junction of the substrate—third lightly doped area reaches up to the surface of the substrate, and the drain junction enters the pinch off state. When the surface layer of the second lightly doped area 123 is removed, the drain has a stronger effect as the channel of a parasitic coupling field effect transistor PJ, which increases the drain resistance. As a result, the on current is reduced significantly for a lower source potential, and the cutoff source voltage decreases.
One task of the present invention is to solve the aforementioned problem by providing a semiconductor device, which has a MOS transistor with a high breakdown voltage and double sidewall insulation films for compatibility in the manufacturing process with a MOS transistor with a low drive voltage and which can inhibit increases in the drain leaking current, decreases in the cutoff source voltage, and other negative effects on the electric characteristics. Another task is to provide the manufacturing method of this semiconductor device.